In a conventional code division multiple access (CDMA) receiver, a received signal is first down converted from a carrier frequency to a more suitable baseband. The baseband is subsequently digitally sampled for further processing. The down converting and digitizing obligates the conventional CDMA receiver to achieve both a frequency lock and a timing lock with transmitted signals broadcast from a transmitter. The digital samples are used by the conventional CDMA receiver for recovery of the transmitted signals.
Referring to FIG. 1, a block diagram of a partial conventional CDMA system 10 is shown. The conventional CDMA system 10 includes a transmitter 12 and a receiver 14. The transmitter 12 has a data source 16, a mixer 18 and a source oscillator 20. The receiver 14 has a mixer 22, an analog to digital converter (ADC) 24, a local oscillator 26, a sampling oscillator 28 and a reference oscillator 30.
Two different processes maintain the receiver 14 in lock with the transmitter 12. A first process is an automatic frequency correction (AFC) process that works to track a frequency of the received signal. A second process is a time tracking process that works to track the timing of the received signal. The conventional CDMA receiver 14 typically generates a reference signal (i.e., F_REF) in the reference oscillator 30 from which all other frequencies are derived, notably a sample clock signal (i.e., F_S) and a local clock signal (i.e., F_LO). The AFC process seeks to adjust the local clock signal F_LO to match a source clock signal (i.e., F_SRC) in the transmitter 12 by adjusting the reference clock signal F_REF. The time tracking process seeks to select and match a received sample (i.e., RX_SAMPLES) with a corresponding transmit sample (i.e., TX_SAMPLES).
Referring to FIG. 2, a time line diagram illustrating an example timing offset for the conventional CDMA system 10 is shown. In the example timing, the AFC process has locked to the source clock signal F_SRC and a slight timing error 32 exists between the transmitted samples TX_SAMPLES and the received samples RX_SAMPLES. Individual RX_SAMPLES are separated by a sample period (i.e., Ts) Typically, the sample period Ts is chosen such that a maximum sampling error of Ts/2 seconds produces a minimal degradation to the system performance. For the conventional CDMA system 10, the sample period Ts is commonly ⅛th of a CDMA chip duration (i.e., Tc/8).
For most scenarios, the Tc/8 sample spacing produces a negligible timing error of Tc/16. However, in some special cases when an input noise is dominated by cross-correlation from the user's own signal or signals from other users, further reduction in the timing error is desirable. In the conventional CDMA system 10, where the AFC process and time tracking process operate independently, once the AFC process locks (i.e., F_LO=F_SRC), the timing error is fixed. In FIG. 2, the spacing between samples is the same but a fixed offset 32 remains between the edges of the transmitted samples and the received samples. The amount of error is random and may be as large as Ts/2.
U.S. Pat. No. 6,266,365 to Wang et al. discloses a CDMA receiver. Wang discloses, “In order to compensate for errors derived from the lower sampling rate, firstly adjustments are made to the phase of the clock signal for sampling the received signal and secondly a new algorithm is applied to adjust the phase of the clock signal used by each DLL for generating its local spreading waveform. In this context, adjustment of phase means change in the position of the leading edge of the clock waveform. It does not mean change of frequency of that waveform, which can be realized by automatic frequency control (AFC).” Biasing the AFC circuitry would be desirable to reduce the time tracking error.
U.S. Publication 2004/0058653 to Dent discloses a chip rate correction in digital transceivers. Dent discloses, “In one exemplary embodiment of the invention, the timing correction circuit generates a frequency offset value based on the timing error so that the local frequency reference is biased, and hence the CDMA chip rate, is gradually altered to correct the timing drift at the penalty of an alteration in the frequency of transmission.” Accounting for timing errors greater than Ts/2 other than through a gradual adjustment would be desirable.